It has become usual in connection with large scale memories to provide an area for redundant memory cells, so that a defective memory cell in the main memory area does not make the entire memory unusable.
It is desirable, in order to reduce the manufacturing costs of large scale memories, to provide accelerated methods of testing the memory cells, to insure that the entire memory cell array operates properly. In order to facilitate the testing, it has been proposed to test a number of memory cells simultaneously within the main memory area, but heretofore it has not been possible to test portions of the redundant memory areas simultaneously with the main memory. Thus, it has been necessary to test the redundant areas separately, which prolongs the testing procedure and renders the finished memory arrays more expensive because of the time and effort required for testing them completely.
Accordingly, it is a principal object of the present invention to provide a method for testing memory areas which have been set aside as redundant, at the same time as the testing of the other memory areas of the main memory. This allows the testing process to proceed more rapidly, and a separate testing procedure is not required for the redundant memory areas.
These and other objects and advantages of the present invention will become manifest by inspection of the following description and the accompanying drawings.
In one embodiment of the present invention, there is provided a control circuit located on the chip in operative association with a single chip semiconductor memory having a redundant semiconductor memory portion, for enabling access to the redundant semiconductor memory area for reading. The control circuit is enabled by the simultaneous occurrence of a select signal, which functions to select a given portion of the main memory area, a second signal indicating that the multiple bit test (MBT) mode is active, and a further signal describing that the redundant memory area has been programmed.